Commit 0d43beda authored by Philipp Schlehuber's avatar Philipp Schlehuber Committed by Alexandre Duret-Lutz
Browse files

game: reimplement print_aiger

* spot/twaalgos/aiger.cc, spot/twaalgos/aiger.hh: Reimplement
print_aiger for speed gain, also heuristics to minimize the number
of gates as well as different encoding types have been added.
* bin/ltlsynt.cc: Make the new options for print-aiger available.
* tests/core/ltlsynt.test: Adjust tests.
parent f5965966
......@@ -13,6 +13,11 @@ New in spot 2.9.4.dev (not yet released)
- ltlsynt learned --print-game-hoa to output its internal parity
game in the HOA format (with an extension described below).
- ltlsynt --aiger option now takes an optional argument indicating
how the bdd and states are to be encoded in the aiger output.
Choices are "ITE" for the if-then-else normal form or "ISOP" for
relying on irreducible sums of products.
Library:
- Historically, Spot labels automata by Boolean formulas over
......
......@@ -93,8 +93,10 @@ static const argp_option options[] =
"print the parity game in the HOA format, do not solve it", 0},
{ "realizability", OPT_REAL, nullptr, 0,
"realizability only, do not compute a winning strategy", 0},
{ "aiger", OPT_PRINT_AIGER, nullptr, 0,
"prints the winning strategy as an AIGER circuit", 0},
{ "aiger", OPT_PRINT_AIGER, "ITE|ISOP", OPTION_ARG_OPTIONAL,
"prints a winning strategy as an AIGER circuit. With argument \"ISOP\""
" conditions are converted to DNF, while the default \"ITE\" uses the "
"if-the-else normal form.", 0},
{ "verbose", OPT_VERBOSE, nullptr, 0,
"verbose mode", -1 },
{ "csv", OPT_CSV, "[>>]FILENAME", OPTION_ARG_OPTIONAL,
......@@ -132,7 +134,7 @@ static bool opt_print_pg = false;
static bool opt_print_hoa = false;
static const char* opt_print_hoa_args = nullptr;
static bool opt_real = false;
static bool opt_print_aiger = false;
static const char* opt_print_aiger = nullptr;
static spot::option_map extra_options;
static double trans_time = 0.0;
......@@ -542,7 +544,7 @@ namespace
// output the winning strategy
if (opt_print_aiger)
spot::print_aiger(std::cout, strat_aut);
spot::print_aiger(std::cout, strat_aut, opt_print_aiger);
else
{
automaton_printer printer;
......@@ -612,7 +614,7 @@ parse_opt(int key, char* arg, struct argp_state*)
opt_print_hoa_args = arg;
break;
case OPT_PRINT_AIGER:
opt_print_aiger = true;
opt_print_aiger = arg ? arg : "INF";
break;
case OPT_REAL:
opt_real = true;
......
This diff is collapsed.
// -*- coding: utf-8 -*-
// Copyright (C) 2017 Laboratoire de Recherche et Développement
// Copyright (C) 2020 Laboratoire de Recherche et Développement
// de l'Epita (LRDE).
//
// This file is part of Spot, a model checking library.
......@@ -39,8 +39,18 @@ namespace spot
/// property is not set, all AP are encoded as inputs, and the circuit has no
/// output.
///
/// \pre In order to ensure correctness, edge conditions have
/// to have the form (input cond) & (output cond). The output cond
/// does not need to be a minterm.
/// Correct graphs are generated by spot::unsplit_2step
///
///
/// \param os The output stream to print on.
/// \param aut The automaton to output.
/// \param mode Determines how the automaton is encoded.
/// "ISOP" Uses DNF.
/// "ITE" Uses the "if-then-else" normal-form
SPOT_API std::ostream&
print_aiger(std::ostream& os, const const_twa_ptr& aut);
print_aiger(std::ostream& os, const const_twa_ptr& aut,
const char* mode);
}
......@@ -47,42 +47,80 @@ diff out exp
cat >exp <<EOF
REALIZABLE
aag 30 1 3 1 26
aag 31 1 3 1 26
2
4 47
4 49
6 57
8 59
61
10 3 5
12 7 9
14 10 12
16 2 5
18 16 12
20 3 4
22 20 12
24 2 4
26 24 12
28 6 9
30 16 28
32 10 28
34 24 28
36 20 28
63
10 7 9
12 5 10
14 12 3
16 12 2
18 4 10
20 18 3
22 18 2
24 6 9
26 5 24
30 26 3
32 4 24
34 32 2
36 32 3
38 7 8
40 16 38
42 10 38
44 23 33
46 15 44
48 27 31
50 19 48
52 35 41
54 33 52
56 50 54
58 37 43
60 48 54
40 5 38
42 40 2
44 40 3
46 21 31
48 15 46
50 17 23
52 35 43
54 50 52
56 27 54
58 37 45
60 27 52
62 23 60
i0 a
o0 b
EOF
ltlsynt --ins=a --outs=b -f 'GFa <-> GFb' --aiger >out
ltlsynt --ins=a --outs=b -f 'GFa <-> GFb' --aiger=ISOP >out
diff out exp
cat >exp <<EOF
REALIZABLE
aag 28 1 3 1 24
2
4 38
6 49
8 56
29
10 6 9
12 5 10
14 7 8
16 15 11
18 4 9
20 5 17
22 21 19
24 2 23
26 3 12
28 27 25
30 7 9
32 4 30
34 5 9
36 35 33
38 3 37
40 6 11
42 5 41
44 43 19
46 2 45
48 27 47
50 4 10
52 5 14
54 53 51
56 3 55
i0 a
o0 b
EOF
ltlsynt --ins=a --outs=b -f 'GFa <-> GFb' --aiger=ITE >out
diff out exp
cat >exp <<EOF
......@@ -94,14 +132,14 @@ aag 16 1 2 2 13
31
31
8 5 7
10 3 8
12 2 8
10 8 3
12 8 2
14 4 7
16 3 14
18 2 14
16 14 3
18 14 2
20 5 6
22 2 20
24 3 20
22 20 2
24 20 3
26 17 25
28 11 26
30 19 23
......@@ -110,7 +148,29 @@ i0 a
o0 b
o1 c
EOF
ltlsynt --ins=a --outs=b,c -f 'GFa <-> (GFb & GFc)' --aiger >out
ltlsynt --ins=a --outs=b,c -f 'GFa <-> (GFb & GFc)' --aiger=Isop >out
diff out exp
cat >exp <<EOF
REALIZABLE
aag 10 1 2 2 7
2
4 18
6 20
14
14
8 4 7
10 5 6
12 11 9
14 2 13
16 4 9
18 3 17
20 2 17
i0 a
o0 b
o1 c
EOF
ltlsynt --ins=a --outs=b,c -f 'GFa <-> (GFb & GFc)' --aiger=ite >out
diff out exp
cat >exp <<EOF
......
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