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//
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// This file is part of Nolimips, a MIPS simulator with unlimited registers
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// Copyright (C) 2003, 2004, 2006 Benoit Perrot <benoit@lrde.epita.fr>
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//
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// Nolimips is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
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//
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// Nolimips is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
/** \file vm/cp0.hh
    \brief Declare Coprocessor 0 class. */
#ifndef VM_CP0_HH
# define VM_CP0_HH

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namespace inst { class Register; }
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namespace vm
{

  /// Coprocessor 0 (control coprocessor) abstraction
  class Cp0
  {
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  public:
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    typedef uint32_t	register_type;

  public:
    /// Coprocessor 0 registers indices
    enum kind_type
      {
	index = 0,		///< Index register
	random = 1,		///< Random register
	entry_lo0 = 2,		///< Entry for even pages
	entry_lo1 = 3,		///< Entry for odd pages
	context = 4,		///< Context register
	page_mask = 5,		///< Page mask register
	wired = 6,		///< Wired register
	error = 7,		///< Status/control register
	bad_vaddr = 8,		///< Bad virtual address register
	count = 9,		///< Count register
	entry_hi = 10,		///< Entry high
	compare = 11,		///< Compare register
	status = 12,		///< Status (kernel/user mode, etc.) register
	cause = 13,		///< Cause of exception register
	epc = 14,		///< Exception program counter
	pr_id = 15,		///< Processor identification
	config = 16,		///< Configuration register (64 bits)
	lladdr = 17,		///< Loaded linked address
	watch_lo = 18,		///< Watch point debug facility, low part
	watch_hi = 19,		///< Watch point debug facility, high part
	x_context = 20,		///< X context register
	reserved0 = 21,		///< (Reserved register)
	reserved1 = 22,		///< (Reserved register)
	debug = 23,		///< Debug register
	depc = 24,		///< Debug exception program counter
	perf_cnt = 25,		///< Performance counter register
	err_ctl = 26,		///< Error control register
	cache_err = 27,		///< Cache error register
	cache_tag_lo = 28,	///< Cache tag/data low
	cache_tag_hi = 29,	///< Cache tag/data high
	error_epc = 30,		///< Error exception program counter
	desave = 31		///< Debug exception SAVE
      };

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  public:
    /// Cause exception codes
    enum exception_type
      {
	interrupt = 0,		///< Interrupt
	tlb_modified = 1,	///< TLB modified
	tlb_load = 2,		///< TLB load
	tlb_store = 3,		///< TLB store
	addr_load = 4,		///< Address error on load
	addr_store = 5,		///< Address error on store
	bus_inst = 6,		///< Bus error on instruction fetch
	bus_data = 7,		///< Bus error on data load or store
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	syscall = 8,		///< System call
	breakpoint = 9,		///< Breakpoint
	reserved_inst = 10,	///< Reserved instruction
	cop_unusable = 11,	///< Coprocessor unusable
	overflow = 12,		///< Arithmetic overflow
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	trap = 13,		///< Trap
	floating_point = 15	///< Floating point exception
      };
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    /** \name Constructor and destructor
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	\{ */
  public:
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    Cp0();
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    /** \} */

  public:
    /// Reset the CPU (set registers to zero)
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    void reset();
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    /** \name Explicit register accessors
	\{ */
  public:
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    void set_count(register_type r);
    register_type get_count() const;
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    /** \} */

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    /** \name Unified register accessors
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	\{ */
  public:
    /// Set the register identified by \a reg to \a r.
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    void set_register(const inst::Register &reg, register_type r);
    /// Return the register identified by \a reg.
    register_type get_register(const inst::Register &reg) const;
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    register_type get_register(kind_type k) const;
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    /** \} */

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    /** \name Exception handling
        \{ */
  public:
    /// Raise an arithmetic overflow exception
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    void raise_overflow();
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    /// Raise an address error on load exception
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    void raise_addr_load();
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    /// Raise an address error on load exception
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    void raise_addr_store();

    void set_fatal_exception();
    bool fatal_exception() const;
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    /** \} */

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  protected:
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    bool fatal_exception_;

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    /// Dedicated registers (32 bits)
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    register_type registers[32];
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  };

} // namespace vm

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#include "vm/cp0.hxx"

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#endif // !VM_CP0_HH