virtual_machine.cc 13.5 KB
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//
// This file is part of Mipsy, a tiny MIPS simulator
// Copyright (C) 2003 Benoit Perrot <benoit@lrde.epita.fr>
//
// Mipsy is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// 
// Mipsy is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
// 
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
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#include "common.hh"

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#include "vm/virtual_machine.hh"

#include "inst/all.hh"

namespace vm
{

  // --------------------------------------------------------------------------
  // Arithmetic instructions
  // --------------------------------------------------------------------------

  void
  VirtualMachine::visit(const inst::Add& add)
  {
    register_t	a = cpu.get_register(add.get_src1 ());
    register_t	b = cpu.get_register(add.get_src2 ());

    register_t	c = a + b;
    cpu.set_register(add.get_dest (), c);
    
    // FIXME: might be accelerated by testing only the sign bit.
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    if ((a < 0 && b < 0 && c > 0) ||
	(a > 0 && b > 0 && c < 0))
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      {
	std::cerr << "Runtime Exception: Overflow" << std::endl;
	exit_set(exit_runtime);
      }
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  }
  void
  VirtualMachine::visit(const inst::Addi& addi)
  {
    register_t	a = cpu.get_register(addi.get_src ());
    int		b = addi.get_imm ();

    register_t	c = a + b;
    cpu.set_register(addi.get_dest (), c);
    
    // FIXME: might be accelerated by testing only the sign bit.
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    if ((a < 0 && b < 0 && c > 0) ||
	(a > 0 && b > 0 && c < 0))
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      {
	std::cerr << "Runtime Exception: Overflow" << std::endl;
	exit_set(exit_runtime);
      }
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  }
  void
  VirtualMachine::visit(const inst::Addu& addu)
  {
    cpu.set_register(addu.get_dest (),
		     cpu.get_register(addu.get_src1 ()) +
		     cpu.get_register(addu.get_src2 ()));
  }
  void
  VirtualMachine::visit(const inst::Addiu& addiu)
  {
    cpu.set_register(addiu.get_dest (),
		     cpu.get_register(addiu.get_src ()) + addiu.get_imm ());
  }

  void
  VirtualMachine::visit(const inst::Sub& sub)
  {
    register_t	a = cpu.get_register(sub.get_src1 ());
    register_t	b = cpu.get_register(sub.get_src2 ());

    register_t	c = a - b;
    cpu.set_register(sub.get_dest (), c);

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    if ((a < b && c > 0) || (a > b && c < 0))
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      {
	std::cerr << "Runtime Exception: Overflow" << std::endl;
	exit_set(exit_runtime);
      }
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  }
  void
  VirtualMachine::visit(const inst::Subu& subu)
  {
    cpu.set_register(subu.get_dest (),
		     cpu.get_register(subu.get_src1 ()) - 
		     cpu.get_register(subu.get_src2 ()));
  }

  void
  VirtualMachine::visit(const inst::Sll& sll)
  {
    uregister_t	a = cpu.get_register(sll.get_src ());
    unsigned	i = sll.get_imm ();
    register_t	c = a << i;
    cpu.set_register(sll.get_dest (), c);

    // FIXME: Check overflow !
  }
  void
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  VirtualMachine::visit(const inst::Sllv& slv)
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  {
    uregister_t	a = cpu.get_register(slv.get_src1 ());
    uregister_t	b = cpu.get_register(slv.get_src2 ());

    register_t	c = a << b;
    cpu.set_register(slv.get_dest (), c);

    // FIXME: Check overflow !
  }

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  void
  VirtualMachine::visit(const inst::Sra& sra)
  {
    register_t	a = cpu.get_register(sra.get_src ());
    unsigned	b = sra.get_imm ();
    register_t	c = a >> b;
    cpu.set_register(sra.get_dest (), c);

    // FIXME: Check overflow !
  }
  void
  VirtualMachine::visit(const inst::Srav& srav)
  {
    register_t	a = cpu.get_register(srav.get_src1 ());
    register_t	b = cpu.get_register(srav.get_src2 ());

    register_t	c = a >> b;
    cpu.set_register(srav.get_dest (), c);

    // FIXME: Check overflow !
  }

  void
  VirtualMachine::visit(const inst::Srl& srl)
  {
    uregister_t	a = cpu.get_register(srl.get_src ());
    unsigned	i = srl.get_imm ();
    uregister_t	c = a >> i;
    cpu.set_register(srl.get_dest (), c);

    // FIXME: Check overflow !
  }
  void
  VirtualMachine::visit(const inst::Srlv& srlv)
  {
    uregister_t	a = cpu.get_register(srlv.get_src1 ());
    uregister_t	b = cpu.get_register(srlv.get_src2 ());
    uregister_t	c = a >> b;
    cpu.set_register(srlv.get_dest (), c);

    // FIXME: Check overflow !
  }

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  void
  VirtualMachine::visit(const inst::Mul& mul)
  {
    register_t	a = cpu.get_register(mul.get_src1 ());
    register_t	b = cpu.get_register(mul.get_src2 ());

    register_t	c = a * b;
    cpu.set_register(mul.get_dest (), c);

    // FIXME: Check overflow !
  }

  void
  VirtualMachine::visit(const inst::Div& div)
  {
    register_t	a = cpu.get_register(div.get_src1 ());
    register_t	b = cpu.get_register(div.get_src2 ());

    register_t	c = a / b;
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    cpu.set_lo(c);

    c = a % b;
    cpu.set_hi(c);
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    // FIXME: Check overflow !
  }
  void
  VirtualMachine::visit(const inst::Divu& divu)
  {
    uregister_t	a = cpu.get_register(divu.get_src1 ());
    uregister_t	b = cpu.get_register(divu.get_src2 ());

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    cpu.set_lo(a / b);
    cpu.set_hi(a % b);
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  }


  // --------------------------------------------------------------------------
  // Binary instructions
  // --------------------------------------------------------------------------

  void
  VirtualMachine::visit(const inst::And& _and)
  {
    register_t	a = cpu.get_register(_and.get_src1 ());
    register_t	b = cpu.get_register(_and.get_src2 ());

    register_t	c = a & b;
    cpu.set_register(_and.get_dest (), c);
  }
  void
  VirtualMachine::visit(const inst::Andi& andi)
  {
    register_t	a = cpu.get_register(andi.get_src ());
    int		b = andi.get_imm ();

    register_t	c = a & b;
    cpu.set_register(andi.get_dest (), c);
  }

  void
  VirtualMachine::visit(const inst::Or& _or)
  {
    register_t	a = cpu.get_register(_or.get_src1 ());
    register_t	b = cpu.get_register(_or.get_src2 ());

    register_t	c = a | b;
    cpu.set_register(_or.get_dest (), c);
  }
  void
  VirtualMachine::visit(const inst::Ori& ori)
  {
    register_t	a = cpu.get_register(ori.get_src ());
    int		b = ori.get_imm ();

    register_t	c = a | b;
    cpu.set_register(ori.get_dest (), c);
  }

  void
  VirtualMachine::visit(const inst::Nor& nor)
  {
    register_t	a = cpu.get_register(nor.get_src1 ());
    register_t	b = cpu.get_register(nor.get_src2 ());

    register_t	c = a | b;
    cpu.set_register(nor.get_dest (), ~c);
  }

  void
  VirtualMachine::visit(const inst::Xor& _xor)
  {
    register_t	a = cpu.get_register(_xor.get_src1 ());
    register_t	b = cpu.get_register(_xor.get_src2 ());

    register_t	c = a ^ b;
    cpu.set_register(_xor.get_dest (), c);
  }
  void
  VirtualMachine::visit(const inst::Xori& xori)
  {
    register_t	a = cpu.get_register(xori.get_src ());
    int		b = xori.get_imm ();

    register_t	c = a ^ b;
    cpu.set_register(xori.get_dest (), c);
  }


  // --------------------------------------------------------------------------
  // Move instructions
  // --------------------------------------------------------------------------
  
  void
  VirtualMachine::visit(const inst::Li& li)
  {
    cpu.set_register(li.get_dest (), li.get_imm ());
  }

  // Store
  void
  VirtualMachine::visit(const inst::Sb& sb)
  {
    register_t	addr = cpu.get_register(sb.get_base ()) + sb.get_offset ();
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    memory.store_byte(addr, cpu.get_register(sb.get_src ()));
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  }

  void
  VirtualMachine::visit(const inst::Sw& sw)
  {
    register_t	addr = cpu.get_register(sw.get_base ()) + sw.get_offset ();
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    memory.store_word(addr, cpu.get_register(sw.get_src ()));
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  }

  // Load
  void
  VirtualMachine::visit(const inst::Lb& lb)
  {
    register_t	addr = cpu.get_register(lb.get_base ()) + lb.get_offset ();
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    cpu.set_register(lb.get_dest (), memory.load_byte(addr));
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  }

  void
  VirtualMachine::visit(const inst::Lbu& lbu)
  {
    register_t	addr = cpu.get_register(lbu.get_base ()) + lbu.get_offset ();
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    unsigned	b = memory.load_byte(addr);
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    cpu.set_register(lbu.get_dest (), b % 256);
  }

  void
  VirtualMachine::visit(const inst::Lw& lw)
  {
    register_t	addr = cpu.get_register(lw.get_base ()) + lw.get_offset ();
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    cpu.set_register(lw.get_dest (), memory.load_word(addr));
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  }

  // --------------------------------------------------------------------------
  // Test instructions
  // --------------------------------------------------------------------------

  void
  VirtualMachine::visit(const inst::Slt& slt)
  {
    if (cpu.get_register(slt.get_src1 ()) < cpu.get_register(slt.get_src2 ()))
      cpu.set_register(slt.get_dest(), 1);
    else
      cpu.set_register(slt.get_dest(), 0);
  }
  void
  VirtualMachine::visit(const inst::Slti& slti)
  {
    if (cpu.get_register(slti.get_src ()) < slti.get_imm ())
      cpu.set_register(slti.get_dest(), 1);
    else
      cpu.set_register(slti.get_dest(), 0);
  }
  void
  VirtualMachine::visit(const inst::Sltu& sltu)
  {
    if ((uregister_t) cpu.get_register(sltu.get_src1 ()) < 
	(uregister_t) cpu.get_register(sltu.get_src2 ()))
      cpu.set_register(sltu.get_dest(), 1);
    else
      cpu.set_register(sltu.get_dest(), 0);
  }
  void
  VirtualMachine::visit(const inst::Sltiu& sltiu)
  {
    if ((uregister_t) cpu.get_register(sltiu.get_src ()) < 
	(uregister_t) sltiu.get_imm ())
      cpu.set_register(sltiu.get_dest(), 1);
    else
      cpu.set_register(sltiu.get_dest(), 0);
  }
  

  // --------------------------------------------------------------------------
  // Branch and jump instructions
  // --------------------------------------------------------------------------

  // Unconditional
  void
  VirtualMachine::visit(const inst::Jmp& jmp)
  {
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    cpu.set_pc(cpu.get_pc() + jmp.get_label());
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  }
  void
  VirtualMachine::visit(const inst::Jr& jr)
  {
    // Close scope
    end_scope();

    cpu.set_pc(cpu.get_register(jr.get_dest()));
  }

  void
  VirtualMachine::visit(const inst::Jal& jal)
  {
    cpu.set_ra(cpu.get_pc());
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    cpu.set_pc(cpu.get_ra() + jal.get_label());
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    // Open scope
    begin_scope();
  }
  void
  VirtualMachine::visit(const inst::Jalr& jalr)
  {
    cpu.set_ra(cpu.get_pc());
    cpu.set_pc(cpu.get_register(jalr.get_dest()));

    // Open scope
    begin_scope();
  }



  // Equality
  void
  VirtualMachine::visit(const inst::Beq& beq)
  {
    if (cpu.get_register(beq.get_src1 ()) == cpu.get_register(beq.get_src2 ()))
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      cpu.set_pc(cpu.get_pc() + beq.get_label());
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  }
  void
  VirtualMachine::visit(const inst::Bne& bne)
  {
    if (cpu.get_register(bne.get_src1 ()) != cpu.get_register(bne.get_src2 ()))
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      cpu.set_pc(cpu.get_pc() + bne.get_label());
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  }

  // Greater
  void
  VirtualMachine::visit(const inst::Bgez& bgez)
  {
    if (cpu.get_register(bgez.get_src ()) >= 0)
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      cpu.set_pc(cpu.get_pc() + bgez.get_label());
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  }
  void
  VirtualMachine::visit(const inst::Bgezal& bgezal)
  {
    if (cpu.get_register(bgezal.get_src ()) >= 0)
      {
	// Open scope
	begin_scope();
	
	cpu.set_ra(cpu.get_pc());
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	cpu.set_pc(cpu.get_pc() + bgezal.get_label());
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      }
  }
  void
  VirtualMachine::visit(const inst::Bgtz& bgtz)
  {
    if (cpu.get_register(bgtz.get_src ()) > 0)
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      cpu.set_pc(cpu.get_pc() + bgtz.get_label());
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  }

  // Lower
  void
  VirtualMachine::visit(const inst::Blez& blez)
  {
    if (cpu.get_register(blez.get_src ()) <= 0)
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      cpu.set_pc(cpu.get_pc() + blez.get_label());
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  }
  void
  VirtualMachine::visit(const inst::Bltz& bltz)
  {
    if (cpu.get_register(bltz.get_src ()) < 0)
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      cpu.set_pc(cpu.get_pc() + bltz.get_label());
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  }
  void
  VirtualMachine::visit(const inst::Bltzal& bltzal)
  {
    if (cpu.get_register(bltzal.get_src ()) < 0)
      {
	// Open scope
	begin_scope();

	cpu.set_ra(cpu.get_pc());	
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	cpu.set_pc(cpu.get_pc() + bltzal.get_label());
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      }
  }


  // --------------------------------------------------------------------------
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  // Data movement instructions
  // --------------------------------------------------------------------------

  void
  VirtualMachine::visit(const inst::Mfhi& mfhi)
  {
    cpu.set_register(mfhi.get_dest(), cpu.get_hi());
  }
  void
  VirtualMachine::visit(const inst::Mflo& mflo)
  {
    cpu.set_register(mflo.get_dest(), cpu.get_lo());
  }
  void
  VirtualMachine::visit(const inst::Mthi& mthi)
  {
    cpu.set_hi(cpu.get_register(mthi.get_src()));
  }
  void
  VirtualMachine::visit(const inst::Mtlo& mtlo)
  {
    cpu.set_lo(cpu.get_register(mtlo.get_src()));
  }


  // --------------------------------------------------------------------------
  // Exception and trap instructions
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  // --------------------------------------------------------------------------

  void
  VirtualMachine::visit(const inst::Syscall&)
  {
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    switch (cpu.get_v0())
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      {
	// print_int (integer: $a0)
      case 1:
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	ostr << cpu.get_a0();
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	break;

	// print_string (buffer: $a0)
      case 4:
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	for (int i = cpu.get_a0(); true; ++i)
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	  {
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	    char b = memory.load_byte(i);
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	    if (b == 0)
	      break;
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	    ostr << b;
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	  }
	break;
	
	// read_string (buffer: $a0, length: $a1)
      case 8:
	{
	  int i = 0;
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	  int c = 0;
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	  for (; (i < cpu.get_a1() - 1) && (c != '\n') && (c != '\r') ; ++i)
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	    {
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	      c = istr.get();
	      if (istr.eof())
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		break;
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	      memory.store_byte(cpu.get_a0() + i, c);
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	    }
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	  memory.store_byte(cpu.get_a0() + i, 0);
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	}
	break;

	// sbrk (size: $a0)
      case 9: 
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	cpu.set_v0(memory.sbrk(cpu.get_a0()));
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	break;

	// exit
      case 10:
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	halt = true;
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	break;
	
      default:
	assertion(!"syscall: Not implemented yet");
      };
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    ostr.flush();
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  }

} // namespace vm