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//
// This file is part of Mipsy, a tiny MIPS simulator
// Copyright (C) 2003 Benoit Perrot <benoit@lrde.epita.fr>
//
// Mipsy is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// 
// Mipsy is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
// 
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
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#ifndef VM_CPU_HH
# define VM_CPU_HH

// FIXME: lack of compatibility
# include <stdint.h>

# include "inst/register.hh"
# include "vm/memory.hh"
# include "vm/table.hh"

namespace vm
{

  typedef int32_t	register_t;
  typedef uint32_t	uregister_t;
  
  class Cpu
  {
  public:
    Cpu()
    {
      reset();
    }

  public:
    void		reset()
    {
      zero = 0;
      at = 0;
      for (unsigned i = 0; i < 2; ++i)
	v[i] = 0;
      for (unsigned i = 0; i < 4; ++i)
	a[i] = 0;
      for (unsigned i = 0; i < 10; ++i)
	t[i] = 0;
      for (unsigned i = 0; i < 9; ++i)
	s[i] = 0;
      sp = Memory::stack_bottom;
      fp = Memory::stack_bottom;
      ra = 0;
      pc = 0;
    }

  public:
    register_t		get_at() const { return at; }
    void		set_at(register_t r) { at = r; }

    register_t		get_v(unsigned i) const
    {
      precondition(i < 2);
      return v[i];
    }
    void		set_v(unsigned i, register_t r)
    {
      precondition(i < 2);
      v[i] = r;
    }

    register_t		get_a(unsigned i) const
    {
      precondition(i < 4);
      return a[i];
    }

    register_t		get_sp() const { return sp; }
    void		set_sp(register_t r) { sp = r; }

    register_t		get_fp() const { return fp; }
    void		set_fp(register_t r) { fp = r; }

    register_t		get_ra() const { return ra; }
    void		set_ra(register_t r) { ra = r; }

    register_t		get_pc() const { return pc; }
    void		set_pc(register_t r) { pc = r; }

    register_t		get_unlimited(int i) const
    {
      // FIXME: precondition: check existence!
      return unlimited.get(i);
    }
    void		set_unlimited(int i, register_t r)
    {
      unlimited.put(i, r);      
    }

    register_t		get_register(const inst::Register& reg) const
    {
      switch (reg.get_kind())
	{
	case inst::Register::zero:	  return zero;
	case inst::Register::at:	  return at;
	case inst::Register::result:	  return v[reg.get_index()];
	case inst::Register::argument:	  return a[reg.get_index()];
	case inst::Register::temporary:	  return t[reg.get_index()];
	case inst::Register::saved:	  return s[reg.get_index()];
	case inst::Register::sp:	  return sp;
	case inst::Register::fp:	  return fp;
	case inst::Register::ra:	  return ra;
	case inst::Register::unlimited:
	  // FIXME: check existence!
	  return unlimited.get(reg.get_index ());
	}
      return zero;
    }

  public:
    void		set_register(const inst::Register& reg, register_t r)
    {
      switch (reg.get_kind())
	{
	case inst::Register::zero:	  break;
	case inst::Register::at:	  at = r; break;
	case inst::Register::result:	  v[reg.get_index()] = r; break;
	case inst::Register::argument:	  a[reg.get_index()] = r; break;
	case inst::Register::temporary:	  t[reg.get_index()] = r; break;
	case inst::Register::saved:	  s[reg.get_index()] = r; break;
	case inst::Register::sp:	  sp = r; break;
	case inst::Register::fp:	  fp = r; break;
	case inst::Register::ra:	  ra = r; break;
	case inst::Register::unlimited:
	  unlimited.put(reg.get_index (), r);
	  break;
	}
    }

  public:
    void			begin_scope()
    {
      unlimited.begin_scope();
    }
    void			end_scope()
    {
      unlimited.end_scope();
    }

  protected:
    register_t			zero;
    register_t			at;
    register_t			v[2];
    register_t			a[4];
    register_t			t[10];
    register_t			s[9];
    register_t			sp, fp;
    register_t			ra;
    register_t			pc;
    Table<int, register_t>	unlimited;
  };

} // namespace vm

#endif // !VM_CPU_HH